2023-06-14 13:25:00
AMD is managing to wrest more and more market share from Intel in the field of data centers, or at least in the part of the sector related to x86 processors. Those of ARM architecture are very strong, although at the moment they are more specific in purpose. Be that as it may, the company has announced the availability of the 4th generation EPYC processors for all its customers and not just the main ones that have been testing them for a while.
This formal introduction also leaves more details about its architecture, some models and their prices. There are three different types of processors announced. Two of them are the same, the Genoa and Genoa X series, the difference of which is that in the Genoa X it adds an additional cache chiplet, which for certain specific computing loads may give them a good performance boost.
Los Genoa X They are composed of three processors: 9184X (16 núcs., 3.5-4.2 GHz, 768 MB hidden tier 3, 320 W, $4928), 9384X (32 N, 3.1-3.9 GHz, 768 MB N3, 320 W, 5529 $) y 9684X (96N, 2.55-3.7GHz, 1152MB N3, 400W, $14,756). It has 128 PCIe 5.0 lanes and can use DDR5-4800 memory on twelve lanes. That’s at least 1.1TB of RAM per processor.
The other series is Bergamo, which in this case is for a more specialized use for cloud computing. They can integrate up to 128 Zen 4c cores divided into four 16-core chips each, so it does not use the same chips as the Ryzen or EPYC Genoa and Genoa X series that have eight cores per chiplet. They have a more compact interior design but with the same power according to AMD as the Zen 4, but with a substantial reduction in consumption to compete with ARM processors.
The announced models are three: 9754 (128 N, 2.25-3.1 GHz, 256 MB N3, 360 W), 9754S (128 N sin multihilo, 2.25-3.1 GHz, 256 MB N3, 360 W), y 9734 (112N, 2.2-3GHz, 256MB N3, 320W). The drawback they have is that they include much less cache per chip, which for the purpose they have should not impact their performance too much. -information that changes quickly with low reuse chance, so the cache has more impact limited-.
Via:
AnandTech.
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