2023-08-11 22:40:00
The cutting-edge chip production sector is considering various ways to improve its performance and consumption because it is no longer useful just to reduce the size of the transistors. It has not been useful for quite some time, but now it is necessary to apply certain techniques that have been talked about at the university level for a few years. One of them is the rear power delivery (backside power delivery) and that Samsung could use in a future revision of its 3nm process or leave it for 2nm.
It’s a technique that Samsung, Intel and TSMC are experimenting with and will introduce into their lithographic processes at various times. In a paper from the VLSI symposium at the end of June, Samsung indicated that the introduction of this way of delivering power to the transistors reduced the area of a processor by 14.8%, while two Arm architecture processors reduced it by 10.6% and 19 %. He did not indicate what chips they were.
That area reduction means the company can play with it to increase the number of transistors and increase their power, which with this rear power delivery would allow for a 10-20% increase in indicated chips while maintaining the same area. But also, when using the rear power delivery, there is a reduction in the length of the connections between components, which allows the use of thicker tracks with less resistance, which improves the delivered current and therefore higher performance.
Backward power management is about moving power delivery to the very bottom of the wafer, where the transistors are built, rather than having to go through layers and layers of the wafer to deliver power to them. Signal integrity is increased by reducing noise, has lower losses, and allows for higher chip density. The disadvantage is that the manufacturing complexity increases, both due to the machinery to be used and the extra steps to be taken in the manufacturing process of the layers.
Via:
Tom’s Hardware.
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