October 21, 2022
“Design teams sometimes spend 5-7 days per round. Cadence Certus provides an optimization and signoff environment that delivers outstanding PPA results in a matter of hours”
The Cadence company launched the Cadence Certus Closure system designed to speed up the closing process of the design circuit in large and complex chips. According to the company, the new solution shortens the closing schedules by 10 times, through the automation of processes such as static scheduling analysis, optimization and signoff, which are currently performed manually and last several months. The chief engineer of the EDA R&D division at Renesas, Yukio Minoda, said that the company used the Cadence Certus closure solution, “and our engineering team achieved a closure time more than six times faster compared to current methodologies.”
Group director of digital and signoff at Cadence, Dr. Chin-Chi Teng, said design teams often spend 5-7 days per round. Cadence Certus provides an optimization and signoff environment that gives exceptional PPA results in a matter of hours.” The new solution includes a hierarchical architecture that works both in a cloud environment and in an internal computing environment, flexible restoration and replacement of only parts that have changed in the design (Incremental Signoff), automatic implementation that reduces the need for multiple and prolonged iterations between multiple teams, improvements in the interactive graphical user interface (SmartHub) and full system integration Cadence Integrity 3D-IC, which allows to close internal paths in heterogeneous processes.
Published in the categories: news, software and electronic design
Posted in tags: cadence
