AMD plans to bring CXL technology to consumer CPUs, or within the next three to five years | XFastest News

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In a recent webinar, AMD unexpectedly revealed its new plan: to bring Compute Express Link (CXL) technology to consumer CPUs in the next three to five years. This means that persistent memory technology will be brought to the memory bus to further improve performance. Share a large memory pool with CXL memory modules and system memory for higher performance, lower latency, and memory expansion capabilities.

Unlike Intel’s previous Optane technology, CXL has gained broad industry support through an open protocol. It is built on the physical and electrical interface of the PCIe standard, which not only enables high-speed and efficient interconnection between CPU and GPU, FPGA or other accelerators to meet the requirements of today’s high-performance heterogeneous computing, but also supports various types of memory. The CXL Alliance was established in 2019, and Intel and AMD are both members, and the CXL specification has now reached version 3.0.

According to TomsHardware, AMD’s webinar covered a number of topics, including AM5 platforms, DDR5 memory, and PCIe 5.0 SSDs. In the Q&A session, when AMD answered “why are storage devices not connected to the memory bus”, Leah Schoeb, senior manager of storage and memory, said that in the next three to five years, the server field will first see persistent memory technology. Join, and then to the consumer space, AMD will ensure that system memory and other storage devices can communicate on the same bus via the CXL protocol.

The relevant person in charge of Phison Electronics also added on this topic, saying that this is another ecosystem type project, which requires everyone to work together to achieve this. These cooperations have promoted the development of PCs in the past few years, and the two sides temporarily Announce anything in the field. The first CPUs to support CXL are coming soon though, with AMD’s EPYC codenamed Genoa and Intel’s Sapphire Rapids processors both having early revisions to the specification built around the PCIe 5.0 interface.

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