Picture of AMD Epyc Genoa with 12 chiplets
Just yesterday the first image of the new SP5 socket (LGA6096) was released and now we see the next generation of EPYC processors without an integrated heat exchanger.
Chip forum member “zhangzhonghao” appears to be the first person to reveal the actual image of the upcoming Zen4 server processor codenamed Genoa. This is the first image that shows all 12 chiplets installed in SP5.
AMD EPYC “Genoa” CPU, Source: Chiphell
EPYC Genoa contains up to 96 concentrates and 192 chains in its entire composition. AMD will release several SKUs with partially broken cores, so just because this processor has 12 chips doesn’t mean all 96 cores will be active.
Each Zen4 CCD measures 72 mm², which is 8 mm² smaller than the Zen3 (similar to the EPYC “Milan” series). The I/O is also small, at 397 mm² compared to 416 mm² on Zen3 EPYC CPUs. Since the SP5 (LGA 6096) package is also 37% larger than the SP3 package, AMD has no problem installing 6 chips on each I/O side.
AMD 16-core EPYC Genoa processor, Source: VideoCardz
AMD’s new SP5 operating system supports up to 12 channels of DDR5 memory and a PCIe Gen5 interface. According to AMD, AMD Genoa is already shipping to early customers. The new EPYC 7004 series is on its way to launch by the end of this year.
| Rumor has it that the specifications of the AMD EPYC series processors | ||||||
|---|---|---|---|---|---|---|
| video cards | 7001 “Naples” | 7002 “Rome” | 7003 “Milan” 7003 “Milan X” | 7004 “Genoa” | 7004 “Bergamo” | |
| 7005 “Taurine” | start | 2017 | 2019 | 2021 | 2022 | 2022 |
| 2023/2024 | building | 14nm Gen. | 7 nm Zen 2 | 7 nm Zen 3 | 5 nm Zen4 | 5 nm Zen4c |
| Jane 5 | Plug | SP3 (LGA4094) | SP3 (LGA4094) | SP3 (LGA4094) | SP5 (LGA-6096) | SP5 (LGA-6096) |
| SP5 (LGA-6096) | Modules/chiplets | 4xCCD | 8xCCD + 1xIOD | 8xCCD + 1xIOD | 12xCCD + 1xIOD | 12xCCD + 1xIOD |
| TBC | ||||||
| Max number of cores | Max hour | TBC | TBC | |||
| TBC | L2 cache per center | 0.5 MB | 0.5 MB | 0.5 MB | 1 megabyte | TBC |
| TBC | L3 cache for CCX | 8 MB | 8 MB | 32MB / 96MB | 32 MB | |
| TBC | ||||||
| TBC | ||||||
| memory channels | Memory support | PCIe tracks | ||||
| TBC | TBC | |||||
Maximum cTDP TBC Source: Changjongu Civil