Intel CEO Pat Gelsinger shared the company’s path and provided details of the company’s upcoming portfolio, including Meteor Lake, Ponte Vecchio GPU, Intel Xeon D-2700 and FPGAs, and outlined its new system manufacturing model
At Hot Chips 34, Intel introduced the latest architectural and packaging innovations that enable the 2D and 3D tile-based chip designs.
In the first keynote speech by an Intel CEO at the Hot Chips Show since (then-former) Gordon Moore in 1995, Intel CEO Pat Gelsinger shared the company’s path and provided details of the company’s upcoming portfolio, including Meteor Lake, Ponte Vecchio GPU, Intel Xeon D-2700 and FPGAs, and outline its new system manufacturing model.
Intel CEO Pat Gelsinger presented tonight at the hot chips 34 conference the company’s progress in the development of Intel Gen Core 14, 15 processors and revealed initial details about the processor that is expected to compete directly with Apple’s M1-M2 series processors. The processor, developed under Code name Lunar Lake, in Intel Haifa, and is adapted to ultra-light laptops with low power consumption of 15 watts or more. Pat Gelsinger also revealed that the company’s future processors are expected to make use of the so-called disaggregated technology, which combines several components and can be compared to a stack of pancakes sitting on top of each other.
Transition from chips to systems
“The industry is entering a new golden age of semiconductors – an era in chip manufacturing that requires a shift from the traditional mindset of the production model to a systems model. Beyond supporting traditional wafer manufacturing, Intel’s systems manufacturing model integrates advanced packaging, an open ecosystem of chips and software components, to assemble and deliver systems in a package that meets the world’s insatiable demand for computing power and immersive digital experiences. Intel is also responding to industry demand with continued advances in process technology and tile-based design.” Gelsinger explains.
Intel previewed the following product architectures from next-generation technologies at Hot Chips 34:
- מעבדי Meteor Lake, Arrow Lake and Lunar Lake processors will enable the construction of personal computers with tile-based chip designs that create efficiency in production, power and performance. This is done using separate CPU, GPU, SoC and I/O tiles stacked in 3D configurations using Intel’s Foveros stacking technology. This platform transformation is strengthened by industry support for the Universal Chiplet Interconnect Express (UCIe) open specification that allows chips designed and manufactured in different process technologies by different vendors to work together when combined with advanced packaging technologies.
- Intel’s graphics processor for the data center codenamed Ponte Vecchio, was built to address compute density in high-performance computing (HPC) workloads and artificial intelligence supercomputers. According to Gelsinger, this architecture takes full advantage of Intel’s open software model, using OneAPI to simplify API abstraction and cross-architecture programming. Ponte Vecchio consists of a number of complex designs expressed in tiles, connected using a combination of Embedded Multiple Beam Interconnection Bridge (EMIB) and advanced Foveros packaging technologies. High-speed MDFI interconnect allows the package to expand up to two stacks, allowing a single package to contain more than 100 billion transistors.
- Xeon D-2700 series and 1700 are designed to address end-use applications for 5G, IoT, enterprise and cloud applications, with special consideration for the power and space constraints common in many real-world applications. These chips will also be integrated with tile-based design technology, including advanced computing cores, 100G Ethernet with a flexible packet processor, embedded crypto acceleration, time-coordinated computing (TCC), time-sensitive networking (TSN) and built-in optimization for AI processes.
- FPGA technology for hardware acceleration, with particular promise for radio frequency (RF) applications. Intel has identified new efficiencies by combining digital and analog chips, as well as chips from different process nodes and manufacturing plants, cutting development time and maximizing flexibility for developers. Intel will share the results of the new chip design approach in the near future.