Supermicro began shipping its H15 generation server portfolio on Wednesday, featuring 6th Gen AMD EPYC 9006 series processors, according to HPCwire.
The new hardware, codenamed “Venice,” utilizes the Zen 6 microarchitecture to target high-density AI, cloud, and enterprise workloads. The launch arrives as AMD transitions its server lineup to a 2nm manufacturing process, aiming to meet the rising demand for agentic AI infrastructure. This transition to TSMC’s N2 process node is expected to provide up to a 2.6x improvement in performance per watt.
Performance gains in AI and throughput
The Venice lineup offers significant architectural jumps over the previous Turin generation. The flagship EPYC 9996 features 256 cores, which represents a 33 percent improvement over EPYC 9005 “Turin” only a generation ago. Tom’s Hardware reported that a dual EPYC 9996 configuration delivered up to 93 percent higher throughput in SPEC CPU 2026’s intrate test compared to a dual EPYC 9965 server.
The 256-core EPYC 9996 delivers 1,024 threads in a 2P configuration. Benchmark data from Dell’s PowerEdge R9825 using two 9996 processors showed the chips running GROMACS benchPEP 1.8x faster than the 384-core EPYC 9965 server. These same chips solved large OpenFOAM meshes 2.6x faster and performed AES-256-GCM encryption 1.7x faster at 6.8TB/s. In one test, a single socket served 76.5M Valkey GET requests per second.
AMD’s new processors also focus on memory and I/O bandwidth to support large language models and AI agents. The 6th Gen EPYC series supports up to 16 channels of DDR5. At the highest supported transfer rate, memory bandwidth for these chips reaches 512 GB/s for RDIMMs and 819 GB/s for MRDIMMs.
PCIe Gen 6 doubles the CPU-to-GPU I/O bandwidth as noted by The Next Platform. Each socket contains a total of 128 lanes via SP8 chips, which provide 64 PCIe 6.0 lanes per IOD along with eight extra PCIe 4.0 bonus lanes.
Supermicro claims its H15 systems offer 2.6 times the memory bandwidth and twice the PCIe bandwidth of previous-generation systems, according to Stocktwits. According to the company, its AMD-based infrastructure is capable of providing up to 1.8 times more tokens per second for host nodes running frontier models than previous-generation AMD CPUs. Supermicro’s H15 portfolio includes the 2U Hyper and CloudDC servers, which have achieved multiple SPEC CPU world records.
Zen 6 architecture optimizes AI and scheduler capacity
The Zen 6 architecture introduces several internal changes. Unlike Zen 5’s unified scheduler, Zen 6 utilizes split integer schedulers to achieve greater capacity, featuring 48 dedicated ALU entries and 96 shared ALU/AGU entries, whereas Zen 5 used an 88 / 56 split for ALU/AGU. The architecture also features Frequency Adaptive Spectrum Technology (FAST), which uses platform telemetry and firmware policies to adjust frequency. AMD says Zen 6 shortens that recovery by reducing branch misprediction latency.
AMD is positioning Venice to address the rise of agentic AI. Mike Clark, Corporate Fellow, senior vice president, and lead Zen architect at AMD, stated during a briefing that while the company did not foresee the current scale of agentic AI, they believed the Core Complex Die would be vital for these workloads.
AMD claims that Nvidia Corp.’s Vera CPU can support up to 3.3 fewer agents per watt than Epyc 6 chips. AMD reports that its processors offer 1.87x as many AI agents per CPU dollar compared to recent Intel Xeon processors.
The architecture utilizes two core types: Zen 6 and Zen 6c. Zen 6 will enable packing 12 cores into each chiplet. AMD can use this design to build a range of processors, from $15,000 192-core enterprise-grade CPUs down to quad-core budget processors priced under $100. The Venice lineup also includes high-frequency “F” SKUs, such as the 96-core, 5.3GHz EPYC 9686F, which showed a 92% lead over Vera in Java SciMark composite scores.
Venice processor demand exceeds previous EPYC generations
AMD indicated that early demand for Venice is the strongest the company has seen for any new generation of EPYC processors. Hardware manufacturers have pledged more than 240 Venice platforms, which is a 20% increase over the commitments for AMD’s fifth-generation Epyc chip, Turin, Data Center Knowledge reported. These commitments include the H15 generation from Supermicro and platforms from partners such as Dell, HPE, Lenovo, Supermicro and Cisco.
The initial rollout focuses on the SP7 platform, with SP8 systems expected to follow in the first half of 2027. TechSpot noted that the SP8 platform will arrive later, in the first half of next year. The SP8 platform will utilize a somewhat smaller CPU socket that measures 2.46 by 3.15 inches.
The EPYC 9006 series includes a wide range of configurations. Pricing for 1,000-unit tray orders scales from $700 for the eight-core EPYC 9016 to $14,904 for the 256-core EPYC 9996, as cited by BigGo Finance. The published lineup runs to 31 Venice SKUs across the SP7 and SP8 platforms.
| Model | Cores | Threads | Max Boost Clock |
|---|---|---|---|
| EPYC 9996 | 256 | 512 | 4.1 GHz |
| EPYC 9686F | 96 | 192 | 5.3 GHz |
| EPYC 9016 | 8 | 16 | Not specified |
Supermicro is also expanding its rack-scale offerings with the Helios and Helion platforms. Helion racks, built for agentic AI, will be available in three versions, including Helion Liquid, a CPU-only, liquid-cooled rack. Stocktwits reported that Supermicro did not disclose specific shipment volumes, customer orders, or expected revenue for these new systems.
Earlier coverage: AMD Debuts Epyc 6 Processors for AI Agent Workloads