May 25, 2022
The training will take place on June 9 and will focus on methods for optimizing the design using Formality software using machine learning techniques (ML-driven Distributed Processing), which accelerate the validation process 5 times.
On Thursday, June 9, 2022, Synopsys will hold a webinar on the application of new methods for optimizing chip designs, which make it possible to accelerate testing and verification processes five times to achieve the required power, performance and chip area (PPA) metrics. ). The training will take place at 20:00 Israel time and will last 60 minutes.
For more information and registration: 5X Faster Equivalence Checking with Formality ML-driven DPX
Synopsys’ Fusion Compiler provides a broad spectrum of aggressive optimization techniques such as retiming, multibit banking and advanced data-path optimization that our designers want to take advantage of to achieve maximum PPA. Our expectation from production quality Equivalence checking is to be able to complete verification with minimal efforts and the fastest turn-around-time.
This presentation details how Formality with ML-driven Distributed Processing (DPX) delivered out of the box verification without the need to scale back optimizations or sacrifice PPA goals.
Speakers:
Avinash Palepu, Product Marketing Manager for Formality and Formality ECO products. Starting with Intel as a Design Engineer, he has held various design, AE management and Product Marketing roles in the semiconductor design and EDA industries. Avinash holds a Master’s degree in EE from Arizona State University and a Bachelor’s degree from Osmania University.
Woo Sung Choe, Principal Engineer at Samsung Electronics in the SLSI division. Over a span of 20 years, he has worked on advanced node ASIC and SoC design of AP, modem, and connectivity system engineering on various Samsung smartphone projects.
For more information and registration:
Posted in categories: events, news, semiconductors
Posted in tags: webinar, synopsis, semiconductors, chips
