The global microelectronics industry is preparing for a critical convergence of hardware standards and artificial intelligence this spring. The JEDEC Solid State Technology Association has announced two major forums in San Jose, California, designed to align the industry on the next-generation memory for AI, server, cloud, and mobile computing.
Scheduled for May 12 and 13, 2026, these events come at a pivotal moment for the semiconductor landscape. As large language models (LLMs) and generative AI continue to scale, the industry is facing a persistent “memory wall”—a bottleneck where data movement between the processor and memory limits overall system performance and energy efficiency. By convening the architects of today’s most powerful chips and clouds, JEDEC aims to standardize the solutions that will define the next decade of computing.
The forums will be split into two distinct focuses: a Mobile/Client/Edge Forum on Tuesday, May 12, and a Server/Cloud Computing/AI Forum on Wednesday, May 13. Both sessions will bring together a rare concentration of industry leaders to navigate the rapidly evolving memory landscape, from the devices in our pockets to the massive clusters powering the modern internet.
Solving the AI Memory Bottleneck
For those of us who have spent time in software engineering, the challenge is clear: compute power has historically outpaced memory bandwidth. To solve this, the industry is moving toward more integrated architectures. One of the most anticipated discussions at the May forums will center on “AI-Driven Memory, Memory-Driven AI,” specifically the journey of LPDDR6-PIM toward the market.
Processing-In-Memory (PIM) represents a fundamental shift in architecture. Rather than moving massive amounts of data from the memory chip to the CPU or GPU for processing—a process that consumes significant time and power—PIM integrates computational capabilities directly into the memory. This represents particularly critical for “Edge AI,” where devices must process complex tasks locally without relying on a constant cloud connection.
The forum’s agenda includes a specific deep dive titled “Unlocking the Potential of Edge AI: Trends, Opportunities, and Growth for Memory,” highlighting the push to make AI more sustainable and responsive at the hardware level.
A Powerhouse Lineup of Industry Architects
The scale of the 2026 forums is reflected in the attendee list. Keynote presentations are expected from the companies that currently dominate the AI infrastructure stack, including AMD, Dell, Google, Intel, Meta, Microsoft, Samsung, and SK Hynix.
Beyond the giants of cloud and chip design, the forums will feature technical perspectives from a broad ecosystem of specialists. The speaker lineup includes representatives from Advantest, Cadence, Eliyan, Everspin, FuturePlus Systems, Keysight, Micron, the MIPI Alliance, MPS, Super Micro, and Synopsys. This cross-section of companies ensures that the resulting standards are compatible across the entire supply chain, from the initial design tools to the final server rack.
| Date | Forum Focus | Primary Target Sectors |
|---|---|---|
| May 12, 2026 | Mobile/Client/Edge | Smartphones, IoT, Edge AI, Client Computing |
| May 13, 2026 | Server/Cloud Computing/AI | Data Centers, Cloud Infrastructure, LLM Training |
The Role of Standardization in a Fast-Moving Market
In the rush to deploy AI, there is often a temptation to build proprietary, “walled garden” hardware. However, JEDEC’s role as a global leader in microelectronics standards acts as a counterbalance, ensuring interoperability. Without these shared standards, the cost of hardware would spike, and the pace of innovation would slow as companies struggled to make different components work together.
Mian Quddus, Chairman of the JEDEC Board of Directors, emphasized the importance of this collaborative approach. “We are delighted to invite industry professionals to join us for a front-row seat to the future of computing,” Quddus said. He noted that supporting the industry through educational outreach is an integral part of the association’s mission.
JEDEC currently operates with more than 100 technical committees and task groups, drawing on volunteers from over 380 member companies. This massive collaborative effort is what allows a new memory standard to be adopted globally across different manufacturers and consumers almost simultaneously.
Key Technical Challenges Under Review
Beyond the excitement of new standards, the forums will address the grueling reality of system design. One of the highlighted presentations, “Navigating System Design Challenges Amid the Rapidly Evolving Memory Landscape,” will likely tackle several critical issues:
- Thermal Management: As memory density increases and PIM adds heat-generating logic to memory chips, cooling becomes a primary constraint.
- Power Consumption: Balancing the high-performance needs of AI with the strict energy budgets of mobile and edge devices.
- Signal Integrity: Maintaining data accuracy at the extreme speeds required by next-generation memory interfaces.
For the engineers and architects attending, these forums are less about marketing and more about the granular details of how the next generation of hardware will actually be built.
Advance registration is required for both events in San Jose, and the association has indicated that space is limited. Interested professionals can find more information and registration details via the official JEDEC website.
The industry will be watching the outcomes of these May sessions closely, as the consensus reached in San Jose will likely inform the hardware roadmaps for the 2027 and 2028 product cycles. The next major milestone following these forums will be the publication of the updated technical standards resulting from these committee discussions.
Do you think PIM will finally break the memory wall, or is the solution in the software? Let us know your thoughts in the comments.
