The simultaneous developments highlight how the island’s semiconductor industry is pushing forward on both manufacturing capacity and materials science. As demand for artificial intelligence processors outstrips supply from chip designers like Nvidia, massive infrastructure investments are rising to meet the bottleneck.
Chiayi Science Park Expansion Adds Two Advanced Packaging Plants
Taiwan Semiconductor Manufacturing Co. (TSMC) is adding two advanced chip packaging plants at the Chiayi Science Park, National Science and Technology Council Minister Wu Cheng-wen announced during a groundbreaking ceremony. The location in southern Taiwan is developing into a major advanced packaging hub for the company.
The first advanced packaging facility at the site has already entered mass production, and a second plant is preparing to start mass production soon. According to National Science and Technology Council Minister Wu Cheng-wen, the groundbreaking event initiated the second phase of development, which encompasses a third and fourth plant.
National Science and Technology Council Minister Wu Cheng-wen stated via Reuters that the groundbreaking marked the start of the second phase, which will include a third and fourth plant.
Once all four facilities are fully operational, the park is projected to generate more than 300 billion Taiwan dollars in annual production value. The expansion is also expected to create more than 9,000 jobs in the region. The rapid scaling of chip-on-wafer-on-substrate technology is directly driven by intense market demand for advanced artificial intelligence hardware from artificial intelligence chip designers like Nvidia.
Epitaxial Interface Engineering Overcomes Two-Dimensional Limits
While packaging plants scale up physical production, academic and corporate researchers are tackling the fundamental physical limits of next-generation materials. Traditional silicon semiconductor technology is approaching physical limits, causing severe short-channel effects such as transistor leakage and reduced control as channels grow thinner.
To continue scaling and improving performance, researchers have focused on single-layer molybdenum disulfide (MoS₂). This two-dimensional material is naturally thin at the atomic level while retaining semiconductor properties, making it an ideal candidate for smaller and more energy-efficient transistors. However, placing a thin gate dielectric layer on top of the material typically creates dielectric-related scattering effects, which disrupt the surface, cause electron transmission to be obstructed, and hamper efficiency.
Balancing Ultra-Thin Insulators with High Carrier Mobility
Instead of growing high-dielectric-constant materials directly onto the rough surface of the molybdenum disulfide, the team inserted a carefully cultivated buffer layer to build a solid foundation first. Using ultra-high vacuum technology, researchers precisely deposited an ultra-thin layer of aluminum on the single-layer MoS₂ surface, then oxidized it to form an aluminum oxide (Al₂O₃) layer roughly 0.42 nanometers thick.
This high-quality atomic-scale foundation supports the uniform growth of the upper hafnium dioxide (HfO₂) dielectric material. The atomic-level thickness of the aluminum oxide interface enhances the quality between the two-dimensional semiconductor and the dielectric layer, effectively lowers electronic transmission obstacles, and successfully balances the two key characteristics of being ultra-thin and maintaining transconductance.
The high-performance single-layer molybdenum disulfide top-gate transistor produced through this epitaxial interface engineering technique exhibits very low leakage currents and excellent operational stability at extremely small sizes, while providing strong gate control capabilities without significant degradation in carrier mobility. The research team successfully combined the two previously mutually exclusive goals of a thin insulating layer versus high carrier mobility, demonstrating the potential for two-dimensional semiconductor devices to move toward practical applications.
This industry-academia collaboration shows that such two-dimensional material transistor research is no longer merely forward-looking academic exploration, but a direction actively laid out by industry leaders as a successor technology route for the post-silicon era. The team's research paper was published in the journal Nature Electronics.
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