A new processor architecture promises to be 10 to 100 times more energy-efficient for tasks in embedded systems.
A startup called Efficient Computer has developed a new C-programmable processor, the Electron E1, designed for extreme energy efficiency in edge computing.
- A new processor, the Electron E1, offers significantly better energy efficiency for embedded systems.
- It utilizes a spatial computing architecture, moving away from the traditional von Neumann model.
- This innovative design minimizes overhead associated with instruction fetching and branch prediction.
- The technology could be crucial for long-lasting, battery-powered devices in remote locations.
There’s a growing need for processors that can operate for extended periods in hard-to-reach places, often on limited battery power. Frustrated with the inefficiencies of existing ultralow-power microprocessors, the founders of Efficient Computer set out to reinvent the general-purpose processor from the ground up, focusing on energy efficiency.
“We’re doing something that has the capability of a CPU but is one or two orders of magnitude more efficient,” said cofounder Brandon Lucia.
Rethinking Processor Design for the Edge
The Electron E1 processor and its accompanying compiler are now making their way to developers and early partners. Lucia stated that the C-programmable processor is achieving 10- to 100-fold better efficiency compared to commercial ultralow-power CPUs for typical embedded systems tasks. These tasks include performing fast Fourier transforms on sensor data and executing convolutions for machine learning applications.
Lucia explained that the key innovation lies in an architecture that can lay out a program’s instructions spatially on a chip. This contrasts with current processors that follow the von Neumann architecture, delivering instructions sequentially from memory.
The von Neumann architecture, dominant for decades, fetches an instruction from memory, processes data as directed, stores the result, and then fetches the next instruction. While seemingly straightforward, this process incurs significant overhead. “Several billion times per second, you’re pulling an instruction in from memory. That operation costs some energy,” Lucia noted.
To prevent processing stalls, modern CPUs also employ techniques like branch prediction, which requires additional logic and further energy consumption. The E1, however, maps instructions as a spatial pathway for data to move through. It’s fundamentally an array of “tiles,” each acting like a stripped-down processor core. These cores can execute instructions but lack the overhead of instruction fetching and branch prediction. The tiles are interconnected via a custom-designed, programmable network.
The E1’s compiler, called the effcc Compiler, reads programs written in languages like C. It assigns each instruction to a specific tile and configures the network to route data through the tiles in the correct sequence. When a program branches, the spatial pattern of tiles adjusts accordingly, described by Lucia as being “like a switch track in a railroad.”
While other dataflow architectures exist, such as Google’s TPUs and Amazon’s Inferentia chips which use systolic arrays, Lucia pointed out that these are often restricted to a subset of possible data paths. The E1’s network fabric, however, supports arbitrary paths, including essential “while loops” or recurrences. This ability to handle feedback paths allows for general-purpose computing, a feat that has eluded many other dataflow architectures.
Todd Austin, a computer science and engineering professor at the University of Michigan, sees chips like the E1 as prime examples of efficient architectures. He noted that they minimize silicon dedicated to non-computational tasks like instruction fetching or data buffering.
Rakesh Kumar, a computer architect at the University of Illinois Urbana-Champaign, praised the team’s “clever work” in achieving extremely low power for general-purpose computing. However, he also highlighted the economic challenges for the startup, citing intense competition in the market for cheap, low-power microcontrollers. The key to success, he predicts, will be identifying a unique capability that customers are willing to pay for.
