2024-01-16 00:27:00
Intel includes introducing RibbonFET GAA transistors and a power supply network on the BSPDN chip starting at 20A (20 angstroms or 2 nm), then improving them with 18A, and then starting to use High-NA EUV tools for an advanced manufacturing node from 18A to offer Features power, performance and terrain, and extremely low cycle time
Intel began receiving ASML’s 0.55 numerical space (high-NA) extreme ultraviolet (EUV) lithography tool this week, which it will use to learn how to use the technology before turning the machines into an advanced production node from 18A in the coming years. In contrast, TSMC is in no rush to adopt High-NA EUV anytime soon, and it could be years before the company jumps on the bandwagon in 2030 or later, according to analysts from China Renaissance and SemiAnalysis. This is according to an article published on the Tom’s Hardware website.
Szehu Ng, an analyst at China Renaissance, wrote: “Unlike Intel’s use of High-NA EUV immediately after the transition to GAA (planned to be integrated into 20A), we expect TSMC to use High-NA EUV During the N1.4 period (an important change in the N1, planned for launch after 2030)”.
Intel includes introducing RibbonFET GAA transistors and a power supply network on the BSPDN chip starting at 20A (20 angstroms or 2 nm), then improving them with 18A, and then starting to use High-NA EUV tools for an advanced manufacturing node from 18A to offer Features power, performance and terrain, and extremely low cycle time.
Intel plans to introduce patterning starting at 20A (which is about to enter mass production) and then High-NA EUV starting at a post-18A production node, which will allow the company to reduce the complexity of its process flow and avoid using EUV double exposures.
However, High-NA EUV lithography tools are much more expensive than Low-NA EUV scanning machines, but High-NA EUV has many details, including a 2x smaller exposure field. As a result, analysts from SemiAnalysis and China Renaissance believe that using High-NA EUV machines will be more expensive than using Low-NA EUV dual exposure, at least initially, so TSMC may not be inclined to use this technology long-term to keep costs low, but at the expense of manufacturing complexity and possibly lower transistor density.
“A double exposure of Low-NA EUV, despite lower efficiency over several exposures, may still cost less than High-NA EUV in the first GAA breakthrough; the higher power of the High-NA EUV light source to increase the CD ( critical dimension) accelerates the wear of the projection optics and photomasks, outweighing the benefits of higher efficiency,” Szehu Ng explained. “This is related to TSMC’s practice of targeting the volume market with the most cost-competitive technologies.”
TSMC began using ultraviolet (EUV) lithography tools to mass-produce chips in 2019, months after Samsung Foundries but years before Intel. Intel wants to be ahead of Samsung and TSMC with High-NA EUV, which may ensure tactical and strategic advantages.
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