2023-07-14 20:35:00
The production of the wafers from which the raw chips are cut is only one part of the manufacturing process for functional chips. The other, and which is equally or more important every day, is the testing and encapsulation process that produces the chips in their final format to be used in any device. TSMC is the one with the most advanced encapsulation processes. Requests for the use of these processes have skyrocketed, so TSMC is accelerating the expansion of its final-stage factories to meet demand.
For example, one of the most requested processes is the chip-on-wafer-on-substrate (CoWoS) process, which is ultimately used by NVIDIA for the A100 and H100 chips, among others. They are high-priced chips, so NVIDIA profits from the additional cost of these advanced packaging processes. Apple uses another advanced packaging technique for the M1/M2 Ultra called direct interconnects between chipsso it will probably also benefit from this production expansion.
Previously it was estimated that the company would expand to processing about 10,000 wafers in these final stage factories, but now there is talk that it will go from 8,000 to 11,000 per month before the end of 2023, while by the end of 2024 it is expected that the processing figure is between 14,500 and 16,000 wafers per month.
The machinery to make this type of advanced packaging is more expensive and is produced to order, so it takes a long time to plan its production to put it in the hands of TSMC. The latest end-stage factory opened by TSMC is Fab 6, inaugurated in mid-June, where it is encapsulated using CoWoS, with wafer-on-wafer (WoW) and integrated branching (InFO).
Via:
Tom’s Hardware.
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